Abstract
As base station architectures shift towards multi-standard, multi-carrier Remote Radio Heads and Active Antenna Modules, system designers are being challenged to reduce cost, power, and area while increasing the number of clocks in the system and still meeting all standards-based requirements. To meet stringent clock specifications, currently deployed systems often include additional filtering or costly discrete clocking components, which is often a sub-optimal trade-off between system performance and circuit cost, area, and power consumption.
A key issue related to accurately specifying clock performance levels is the 'edge sensitive' nature of sampled systems, where a sampled system is defined as any device where the output signal phase alignment is related to the phase of the clock which samples the input signal. ADCs, DACs, LO synthesizer clock inputs and hard-switching mixers are all examples of devices which are sensitive to the noise at the clock's threshold crossing; therefore it is essential to accurately measure the phase noise at the threshold crossing of the clock signal. A result of the sampling process is that aliasing occurs on the clock signal and all of the noise associated with that clock at the threshold crossing. Frequency planning is an important technique to avoid selecting frequencies at which aliased spurs fall into the wanted frequency band. Use of proper measurement techniques such as observing the spectral content of a clock following a high quality limiting amplifier to isolate phase noise at the threshold crossing enables system designers to more accurately account for spurious noise and aliasing effects in sampled systems. In addition, careful phase planning of system clocks can significantly reduce spurious coupling between clocks.
This white paper reviews the basic concepts of phase noise, contrasting continuous with discretely sampled phase noise, discusses frequency aliasing, and explores phase planning techniques that aid designers to address high-density clocking requirements in next-generation base station systems. A clocking architecture that utilizes these techniques is finally presented as an example of how the clocking requirements for a 2T2R base station are addressed by a single high-density clocking solution.
About PMC
PMC-Sierra®, the premier Internet infrastructure semiconductor solution provider, offers its customers technical and sales support worldwide through a network of offices in North America, Europe, Israel and Asia. PMC-Sierra provides semiconductor solutions for Enterprise and Channel Storage, Wide Area Network Infrastructure, Fiber To The Home, and Laser Printer/Enterprise market segments. The Company is publicly traded on the NASDAQ Stock Market under the PMCS symbol. For more information, visit www.pmc-sierra.com.
About the Authors
Mark Hiebert is a Leader in the Mixed Signal Design Group at PMC-Sierra.
Ben Lake is a Senior Applications Engineer in the Broadband Wireless Division at PMC-Sierra.
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